Design and Implementation of Compact Booth Multiplier for Low power, Low Area & High Speed Applications

Presently, the design of a compact multiplier is playing a vital role in the stream of VLSI signal processing, DSP, Modern wireless communication etc. The main goal of this proposal is to design a compact booth multiplier by using modified radix4 recoding and an efficient finite state machine (FSM) to achieve small chip size and low delay utilization. In the existing technique, compression based booth multiplier is designed by using carry look ahead adder, multiplexer, booth encoder and partial product generator (PPG). It requires more resource utilization (area) and the performance characteristics is very less in the existing booth multiplier. To come up with a solution to this problem, modified radix4 algorithm with an optimized FSM design is used to construct the compact booth multiplier. Simulation and synthesis is performed by applying the ModelSim and Xilinx 13.1 based on Verilog HDL. FPGA spartan6 LX9 board is used for implementation.